1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of fabrication thereof and particularly to highly reliable semiconductor devices and methods of fabrication thereof.
2. Description of the Background Art
As a material for a line for large scale integration circuits (LSIs), aluminum has conventionally been employed. However, as LSIs are increasingly microfabricated and operated more rapidly, aluminum is being replaced with copper (Cu), a material smaller in electrical resistance. Employing Cu as a material for a line for LSIs allows electrical resistance to be reduced and also the line to be microfabricated, and also allows LSIs to operate faster. Cu, however, is diffusible into insulation film. If Cu diffuses into insulation film, the line would be impaired in reliability. Furthermore, Cu reacts with plasma ions very slowly. As such, if etching is employed to form the line, sufficient productivity cannot be achieved.
To address these disadvantages in recent years a Cu line is formed in damascene. If typical damascene is employed to form a Cu line the line is formed as follows:
Initially an underlying line of Cu is covered with a liner film, an interlayer insulation film and an anti-reflection film deposited in layers. Subsequently, resist for forming a via hole is deposited on the anti-reflection film and typical photolithography and etching are employed to provide the interlayer insulation film with the via hole so that the via hole has a bottom has a bottom surface exposing the liner film. The resist for forming the via hole is then removed and thereafter resist for forming a trench is deposited on the anti-reflection film and in the via hole and typical photolithography and etching are employed to provide the interlayer insulation film with a trench. Then the resist for forming the trench and the anti-reflection film are removed and thereafter the liner film exposed at the bottom surface of the via hole is etched to expose the underlying line. Then a Cu oxide film of a surface of the underlying line exposed at the via hole's bottom surface, residue (or polymer) produced in etching the liner film, and the like are removed by performing argon (Ar) sputter etching, annealing in an ambient of hydrogen (H2), a plasma process, wet-etching, or the like. Then, barrier metal is deposited on the via hole and trench's sidewall and bottom surfaces and the interlayer insulation film. Then, a thin Cu film serving as a film that shields plating is deposited on the barrier metal, and plating is employed to deposit a Cu film on the via hole and trench's sidewall and bottom surfaces, and the interlayer insulation film. Then, excessive Cu film and barrier metal on the interlayer insulation film is chemically mechanically polished and thus removed to complete the Cu line.
The Cu line thus obtained, however, is more breakable as voids are caused. More specifically, when high temperature is attained for example in a thermal treatment, an actual environment of use, or the like, thermal stress is caused between the interlayer insulation film and the Cu line. For a conventional Cu line, the underlying line's surface and the via hole's side wall are in contact with each other at a right angle, and a portion at which the underlying line's surface and the Cu line's bottom contact each other tends to experience concentrated thermal stress.
Furthermore in the via hole the Cu line passes a current, which passes through the portion at which the underlying line's surface and the Cu line's bottom contact each other, and flows to the underlying line, which has a larger area in cross section than the via hole. As such, the portion at which the underlying line's surface and the Cu line's bottom contact each other tends to experience a concentrated current.
Thus the portion at which the underlying line's surface and the Cu line's bottom tends to experience concentrated thermal stress and current. As such, the portion provides a point initially causing voids. For a conventional Cu line, the underlying line and the Cu line contact each other in a plane. As such, the lines mutually contact over an insufficient area, and the line is disadvantageously more breakable. Furthermore, between the Cu line and the underlying line there is a disadvantageously large electrical resistance.
To address this, a method of forming a line that allows a Cu line and an underlying line to mutually contact over an increased area is disclosed for example in Japanese Patent Laying-Open No. 2002-064138. As described in the document, the line is formed as follows:
On a first layer line of Cu a copper diffusion preventing insulation film is deposited and thereafter an interlayer insulation film is deposited. Subsequently on the interlayer insulation film a resist film is deposited and used as a mask to expose a surface of the first layer line by anisoptropically etching the interlayer insulation film and the copper diffusion preventing insulation film. Furthermore, the first layer line's exposed surface is further etched to form a contact hole having a bottom deeper than the first layer line's surface. Subsequently a barrier layer is deposited on the interlayer insulation film including the contact hole's interior. Subsequently, a tantalum (Ta) film is deposited on the barrier layer. Subsequently, the Ta film and barrier layer outside the contact hole is chemically mechanically polished and thus removed to form a plug on the first layer line.
In the method disclosed in the publication the interlayer insulation film and the first layer line are etched to form a hole which in turn has a plug introduced therein. As such, the plug has a bottom surface and a partial side surface in contact with the first layer line. More specifically, the plug and the first layer line can mutually contact stereoscopically and hence over an increased area.
Other than the above publication, for example Japanese Patent Laying-Open Nos. 2001-077195, 2000-114261, 07-014836 and 2000-133711 also disclose etching an interlayer insulation film and an underlying line to form a hole which is in turn provided therein with a conductive layer.
As disclosed in Japanese Patent Laying-Open No. 2002-064138, resist remaining in the hole and residue (or polymer) of the copper diffusion preventing insulation film are removed, and this requires that after the interlayer insulation film and the first layer line are etched the hole's interior be washed. However, the hole's interior is washed with a solution having a property dissolving Cu. As such, in the cleaning the hole the first layer liner is wet-etched. This results in the first layer line having a hole larger in diameter than that in the interlayer insulation film. In other words, the first layer line has a hole having an internal wall with a recess. At this recess the barrier layer and the Ta film are hardly deposited (or tend to be discontinuous). As such, the recess provides a point initially causing voids, which tend to increase electrical resistance and render the line more breakable. This results in a semiconductor device impaired in reliability.